In a hierarchical cache management system, a modified cache line in an on-chip cache, such as an L2 cache, may be written to an intermediary memory device, such as a last level cache, when evicted from the L2 cache, before being written to the main memory. If a write back is performed to a spin-transfer torque magnetic random-access memory (STT-RAM) operating as the intermediary memory device, to minimize the number of bits written, a partial write may be performed where only the dirty bits in the cache line are written to the STT-RAM memory, which reduces energy needed for the write by writing fewer bits in a manner that has no effect on the performance of the write.
Further, when the L2 cache has new data and the last level cache and main memory have older data, then when evicting data in the L2 cache, the last level cache may be bypassed and the new data from the L2 cache may be written directly to the main memory. An alternative technique is to write the new data from the L2 cache to the last level cache.